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Top Level Design
หัวข้อนี้จะเป็นการรวมโมดูล Logic gate ที่เขียนไปข้างต้นเป็น S-R Flip flop 1 ตัว ดังรูป
STEP 3.2 : Top Level Design
1.
สร้างไฟล์ Add source → Design source → name : lab00_part3_RS_ff แล้วคลิกขวา set as top
2.
ทำตามผู้สอนเพื่อเสริมความเข้าใจ จะได้ผลลัพธ์ดังภาพ
หมายเหตุ
คำสั่งที่ทำตามต้องส่งด้วย
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Top-level Simulation
Last modified
2yr ago
